发明名称 A MASTER-SLAVE DELAY LOCKED LOOP FOR ACCURATE DELAY OF NON-PERIODIC SIGNALS
摘要 The present invention involves an electrical component interface system. The system includes clocking circuitry to provide a clock signal. A sending component provide a non-periodic strobe signal and a data signal responsive to the clocking signal. A receiving component receives the strobe signal and data signal. The receiving component includes delay circuitry to delay the strobe signal so as to position edges of the strobe signal with respect to data cells of the data signal. The delay circuitry includes a loaded delay elements and DC level restoration circuitry to control the load of the loaded delay element. The delay elements may be a series of inverters loaded with RC loads. The DC level restoration circuitry may be pulse generation circuitry.
申请公布号 EP1025644(A1) 申请公布日期 2000.08.09
申请号 EP19980934260 申请日期 1998.07.07
申请人 INTEL CORPORATION 发明人 MOONEY, STEPHEN, R.
分类号 G06F1/10;G11C7/22;H03K5/135;H03L7/081;H04L7/00;H04L7/02;H04L7/033;(IPC1-7):H03L7/00 主分类号 G06F1/10
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