发明名称 |
Bias stabilization circuit |
摘要 |
The present invention relates to a bias stabilization circuit, specifically to a bias stabilization circuit for minimizing the current variations of amplification transistors caused by variations of device parameters which occur during the manufacturing of high-frequency integrated circuits using field-effect transistors, and caused by variations of supply voltage and temperature. In the present invention, the above problem is solved by configuring a level shifter circuit between the drain node and the gate node of the reference voltage generation transistor. Further, by using a constant current source utilizing a depletion transistor and series feedback resistors as a reference current, this circuit becomes stable against the variations of the device parameters as well as the variations of the temperature and supply voltage.
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申请公布号 |
US6100753(A) |
申请公布日期 |
2000.08.08 |
申请号 |
US19980137886 |
申请日期 |
1998.08.21 |
申请人 |
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE |
发明人 |
LEE, CHANG SEOK;KIM, MIN GUN;LEE, JAE JIN;PYUN, KWANG EUI |
分类号 |
G05F3/24;(IPC1-7):G05F1/10 |
主分类号 |
G05F3/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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