发明名称 Product-sum calculation circuit constructed of small-size ROM
摘要 There is provided is a product-sum calculation circuit which can be constructed of a ROM having a small capacity. In this product-sum calculation circuit, when multiplier selection signals A0 through A2 select X as a multiplier, a second selector circuit 103 selects a product CkxX obtained by multiplying a multiplicand Ck by the multiplier X and outputs the same to an output control circuit 104. In this case, the output control circuit 104 outputs the product CkxX without shifting the same. When the multiplier selection signals A0 through A2 select (2n)X as the multiplier, the second selector circuit 103 selects the product CkxX obtained by multiplying the multiplicand Ck by the multiplier X and outputs the same to the output control circuit 104 similar to the case where the multiplier X is selected. In this case, the output control circuit 104 outputs (2n)-fold value of (CkxX) by shifting leftward the product CkxX by n bits. Therefore, merely by storing (CkxX) in a data storage circuit 102, a (2n)-fold output of (CkxX) can be obtained.
申请公布号 US6101522(A) 申请公布日期 2000.08.08
申请号 US19980086486 申请日期 1998.05.29
申请人 SHARP KABUSHIKI KAISHA 发明人 SATO, YUICHI
分类号 G06F7/52;G06F7/523;G06F7/53;G06F17/10;(IPC1-7):G06F7/00 主分类号 G06F7/52
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