| 摘要 |
An integrated circuit for error correction takes advantage of a novel data representation ("tower representation") for a selected finite Galois field. Using this representation, novel circuits which utilize the hierarchical structures in the subfields of the selected finite Galois field can be constructed. In one embodiment, GF(256) multipliers, GF(256) multiplicative inverse circuits, GF(256) logarithm circuits can be constructed out of GF(16) multipliers, GF(16) multiplicative inverse circuits and other GF(16) components. These GF(16) components, in turn, can be constructed from still simpler GF(4) components. In that embodiment, a user-programmable burstlimiter is provided. In that embodiment also, a novel quadratic equation solver is provided.
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