发明名称 |
Method and apparatus for improvement of sparse matrix evaluation performance |
摘要 |
A device for reducing evaluation time of a matrix representing an electrical circuit. Conductance values of each circuit component in the circuit are written to corresponding models utilizing non-blocking writing techniques. The matrix is represented by a reduced memory structure where each matrix node is represented by a matrix element structure having at least one pointer to a conductance value contained in a model structure corresponding to a circuit component that contributes to a value of the matrix node. A set of rows or columns of the matrix are then processed to calculate final matrix node values independently.
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申请公布号 |
US6101323(A) |
申请公布日期 |
2000.08.08 |
申请号 |
US19980116010 |
申请日期 |
1998.07.15 |
申请人 |
ANTRIM DESIGN SYSTEMS, INC. |
发明人 |
QUARLES, THOMAS L.;LIEBMANN, S. PETER;SPRUIELL, LESLIE D. |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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