| 摘要 |
A phase detector circuit comprising a control circuit, a pump-up circuit and a pump-down circuit. The control circuit may be configured to generate a control signal in response to (i) a data signal, (ii) a half-rate clock signal, and (iii) a quadrature of the half-rate clock signal. The pump-up circuit may be configured to generate a pump-up signal in response to (i) the data signal, and (ii) the control signal. The pump-down circuit may be configured to generate a pump-down signal in response to (i) the pump-up signal and (ii) the control signal.
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