发明名称 |
Self-aligned silicided MOS transistor with a lightly doped drain ballast resistor for ESD protection |
摘要 |
A MOS transistor with a self-aligned silicide and a lightly doped drain ballast resistor for ESD protection on a semiconductor substrate is formed with the method in the present invention. The ESD protection devices in a ESD protective region are formed at the same time with the forming of the NMOS, PMOS, or both in a functional region. The transistors with a lightly doped drain (LDD) structure and an ultra-shallow junction can be manufactured. The short channel effect and it's accompanying hot carrier effect is eliminated. ESD damage from external connections to the integrated circuits are kept from the densely packed devices. The self-aligned silicide (salicide) technology employed in the present invention for forming low resistance contacts provides high operation speed with low heat generation. Integrated circuits with ESD hardness and high circuit operation speed of the functional devices are provided by the semiconductor manufacturing process employing the method disclosed.
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申请公布号 |
US6100127(A) |
申请公布日期 |
2000.08.08 |
申请号 |
US19970990167 |
申请日期 |
1997.12.12 |
申请人 |
TEXAS INSTRUMENTS - ACER INCORPORATED |
发明人 |
WU, SHYE-LIN |
分类号 |
H01L21/8234;H01L27/02;H01L27/088;(IPC1-7):H01L21/823;H01L21/336 |
主分类号 |
H01L21/8234 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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