发明名称 |
Method for forming self-aligned silicide layers on sub-quarter micron VLSI circuits |
摘要 |
The present invention discloses a method to manufacture a self-aligned silicide layer on a substrate. A metal oxide semiconductor (MOS) device and a shallow trench are fabricated in the substrate. The device has a gate structure, spacers of the gate structured and doping regions. The shallow trench is refilled with silicon oxide material for isolation. A silicon layer is nonconformally deposited on the top surface of the gate structure, the spacers and the doping regions by using a physical vapor deposition (PVD) process, such as ion metal plasma (IMP) process. The IMP process, like a sputtering process, is to ionize a silicon material or a refractory-metal material to silicon ions or metal ions and the ions are biased to anisotropically deposit on the top surface of the substrate. A refractory metal layer is defined on the top surface of the silicon layer by the IMP technology. A two-step thermal annealing process, such as rapid thermal annealing (RTA) process is performed to convert the silicon layer and the refractory metal layer into a silicide layer. Since the silicon layer serves as a silicon source for the salicide process, the silicide layer can form on the spacers and the silicon oxide material of the trench.
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申请公布号 |
US6100191(A) |
申请公布日期 |
2000.08.08 |
申请号 |
US19980059687 |
申请日期 |
1998.04.14 |
申请人 |
UNITED MICROELECTRONICS CORP. |
发明人 |
LIN, TONY;LUR, WATER;WU, JIUN-YUAN;LU, HSIAO-LIN |
分类号 |
H01L21/285;(IPC1-7):H01L21/44 |
主分类号 |
H01L21/285 |
代理机构 |
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主权项 |
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地址 |
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