发明名称 |
Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process |
摘要 |
An integrated circuit fabrication process is provided for using a dual salicidation process to form a silicide gate conductor to a greater thickness than silicide structures formed upon source and drain regions of a transistor. A high K gate dielectric residing between the gate conductor and the substrate substantially inhibits consumption of the junctions during the formation of the silicide gate conductor. In an embodiment, a relatively thick layer of refractory metal is deposited across a transistor arranged upon and within a silicon-based substrate. The transistor includes a polysilicon gate conductor arranged upon a portion of a high K gate dielectric interposed between a pair of source and drain junctions. The refractory metal is heated to convert the polysilicon gate conductor to a silicide gate conductor. After removing the gate dielectric from the source and drain regions, a relatively thin layer of refractory metal is deposited across the topography and heated to form silicide structures upon the source and drain regions.
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申请公布号 |
US6100173(A) |
申请公布日期 |
2000.08.08 |
申请号 |
US19980116066 |
申请日期 |
1998.07.15 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
GARDNER, MARK I.;FULFORD, JR., H. JIM;MAY, CHARLES E. |
分类号 |
H01L21/28;H01L21/285;H01L21/336;H01L29/51;(IPC1-7):H01L21/320 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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