| 摘要 |
A transversal filter (20) has a plurality of variable delay lines each having multiple voltage controlled delay stages in series, with one of the variable delay lines having a clock input (54), and the other variable delay lines having data signal inputs. A phase comparator (150) is coupled to the output of two non-adjacent stages of the variable delay lines having the clock input. A feed-back circuit (25) is coupled to the comparator and provides voltage signals to the voltage controlled delay stages of all of the variable delay lines, such that adjacent stages in a particular delay line are delayed in time equal fractions of a clock cycle from each other, and so that all delay lines are running on the same clock. A voltage weighing circuit (40) is provided for shaping the voltage outputs of the data signal variable delay lines and the weighing circuit is coupled to the delay line stages by switches (128) which are activated when a data signal is propagated through a delay line stage. Where positive pulse, zero pulse, and negative pulse in puts are provided to the transversal filter along with a clock signal, and where the delay lines of the transversal filter have four or more active stages, a substantially raised cosine B3ZS encoded waveform which can be transmitted over a coaxial cable without requiring line build-out can be provided from an incoming B3ZS encoded DS3 signal.
|
