发明名称 |
Fpga integrated circuit having embedded sram memory blocks and interconnect channel for broadcasting address and control signals |
摘要 |
A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes a plurality of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each embedded memory block has an address port for capturing received address signals and a controls port for capturing supplied control signals. Interconnect resources are provided including a Memory Controls-conveying Interconnect Channel (MCIC) for conveying shared address and control signals to plural ones of the memory blocks on a broadcast or narrowcast basis. |
申请公布号 |
AU2854700(A) |
申请公布日期 |
2000.08.07 |
申请号 |
AU20000028547 |
申请日期 |
2000.01.20 |
申请人 |
LATTICE SEMICONDUCTOR CORPORATION |
发明人 |
OM P. AGRAWAL;HERMAN M. CHANG;BRADLEY A. SHARPE-GEISLER;BAI NGUYEN |
分类号 |
H03K19/177 |
主分类号 |
H03K19/177 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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