| 摘要 |
PURPOSE:To decrease the rise time and fall time of output signals by using a circuit structure in which input/output signal pads connected with input/output buffers have smaller areas than other pads so as to decrease parasitic capacitance around the input/output pads. CONSTITUTION:An ECL integrated circuit 1 includes a cell array 2, input/output buffer arrays 3, conventional square signal pads 4, 5 and 6, and smaller square signal pads 7 and 8. Each output buffer 31 has an input terminal 32 connected with a signal line from the cell array and an output terminal 33 connected with both a signal pad and a static protective element. The output terminal has capacitive elements connected: they are the parasitic capacitance C1 between the signal pad and the substrate, the parasitic capacitance C2 between the substrate and the conductor from the output buffer and the pad, and the equivalent capacitance C3 corresponding to the protective element. According to this configuration, it is possible to decrease rise and fall time. |
