发明名称 PHASE LOCK DETECTOR OF PHASE LOCKED LOOP
摘要 PURPOSE: A phase lock detector is provided to avoid the use of passive devices and reduce the production cost by changing the state of a phase lock signal when maintaining the lock state more than the predetermined number of times. CONSTITUTION: A window signal generator(211) generates a window signal having a pulse width corresponding to a phase difference in response to an input signal. A delay circuit(212) delays an output signal frequency-divided by a frequency divider. A first detector(220) detects whether the frequency-divided delay signal exists in the pulse width of the window signal and generates a first detection signal and a second detection signal compensatory to the first detection signal. A toggle unit(270) generates a toggle signal based on a basic clock of the input signal.
申请公布号 KR20000050504(A) 申请公布日期 2000.08.05
申请号 KR19990000428 申请日期 1999.01.11
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 KIM, GYUNG NAM
分类号 H03L7/095;(IPC1-7):H03L7/095 主分类号 H03L7/095
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