HIGH-INTEGRATED DRAM SEMICONDUCTOR DEVICE CONNECTED TO LOW-INTEGRATED DRAM CONTROLLER DEVICE

摘要

PURPOSE: A high-integrated DRAM semiconductor device connected to a low-integrated DRAM controller device is provided to extend a memory capacity by connecting a low-integrated DRAM controller device to a high-integrated semiconductor memory device. CONSTITUTION: Low address bits are inputted to pads(410-421). Address buffers(430-441) converts a voltage level of inputted low address bits into a voltage level suitable to a DRAM semiconductor device(401) and inputs the converted low address to a low decoder(451). A low decoder (451) decodes the inputted low address and enables word lines designated by the low address. A decoding unit(453) decodes the inputted low address and transmits the decoded low address to first and second logic units(455, 456). A control terminal of the first logic unit(455) is connected to a power supply voltage, and a control terminal of the second logic unit(456) is connected to a ground voltage. Since first and second logic units(455, 456) are always activated, and first and second logic units(455, 456) transmit the low address outputted from the decoding unit(453) to word lines.