发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To secure both the speed and stability of locking by selecting and using error signals whose duty factors are different in accordance with a phase pulling stage. SOLUTION: 1st and 2nd pulse generating parts 7 and 8 in a phase difference detector 3 respectively generate pulse trains according to comparison results of a phase comparing part 1. A selector 9 selects one between them according to a control signal. For instance, the part 7 generates a cyclic pulse whose duty factor is small and the part 8 generates a cyclic pulse whose duty factor is large. When power is inputted or when the circuit is started from an input clock disconnection state, phase pulling control is performed with a pulse with a large duty factor. Since a voltage controlled oscillator 5 operates in accordance with the integration of an error signal outputted from the part 1, even though the locking speed increases in such a case, pulling stability is sacrificed. Once locking is completed, control is performed with a pulse with a small duty factor to increase stability.
申请公布号 JP2000216674(A) 申请公布日期 2000.08.04
申请号 JP19990012447 申请日期 1999.01.20
申请人 NEC CORP 发明人 YOSHIMURA MINORU
分类号 H03L7/085 主分类号 H03L7/085
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