发明名称 FORMATION OF VIA HOLE OF SEMICONDUCTOR DEVICE
摘要 <p>PROBLEM TO BE SOLVED: To form a via hole without causing increase in the electrical resistance, and in addition, to suppress the occurrence of leakage currents. SOLUTION: A first step via hole 5 is formed through an SiO2 layer, an etch-stopping layer 2, and a Cu layer 1 and a second-step via hole 6 which is stopped at the etching stopping layer 2 is formed into the layer 2 continuously from the via hole 5 by peeling a resist layer 4. Then the via holes 5 and 6 are cleaned, and a barrier film 7 is formed through sputtering. Since overetching time is shortened, a Cu-Cu connection suppresses effectively an increase in electrical resistance and prevents leakage currents.</p>
申请公布号 JP2000216248(A) 申请公布日期 2000.08.04
申请号 JP19990016258 申请日期 1999.01.25
申请人 NEC CORP 发明人 UENO KAZUYOSHI
分类号 H01L23/52;H01L21/3205;H01L21/768;H01L23/522;H01L23/532;(IPC1-7):H01L21/768;H01L21/320 主分类号 H01L23/52
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