| 摘要 |
<p>PROBLEM TO BE SOLVED: To enable phase matching, without being influenced by the change of clocks and to insure quality in multistage connection by providing a transmitter with a delay circuit to which frame structure data is inputted, while being synchronized with a frame pulse and which synchronizes it with a control signal from a receiver and outputs it. SOLUTION: A transmitter makes input data a prescribed data structure through a series of processing and then inputs data subjected to inverse Fourier transform processing with an IFFT circuit 8 to a data delay circuit 9 with a FIFO configuration. The circuit 9 resets a write pointer with a frame pulse generated by a framing circuit 5, resets a reading pointer with a control effective signal from a receiver to perform reading, performs D/A conversion of delay data, subsequently performs orthogonal modulation on it and transmits it. It is possible to eliminate data errors and data omissions due to step out without synchronizing the clock phases of the transmitter and the receiver, by providing a simple delay circuit in this way.</p> |
