| 摘要 |
PROBLEM TO BE SOLVED: To provide logical synthesis restriction generation and processing device and method therefor for generating restriction for properly distributing restrictions on a pass spread over between blocks in the case of optimizing hardware hierarchically designed by blocks for every block. SOLUTION: A circuit is inputted from a circuit connection information storing part A11 and a circuit delay information storing part A12, a timing analysis part A7 executes the timing analysis of the whole circuit based on restriction inputted from a delay distributing restriction storing part A10 and a delay restriction distributing part A8 finds out the ratio of a block delay value obtained by removing the delay value of the circuit to be optimized at its logical synthesis, distributes logical synthesis delay restriction obtained by subtracting the delay value of a circuit no to be logically synthesized from the pass restriction by the ratio to each block as logical synthesis delay restriction and outputs the logical synthesis delay restriction to a logical synthesis restriction storing part A13.
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