发明名称 SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR TESTING METHOD
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor memory device which assures a shorter testing time. SOLUTION: A test pattern generation circuit 1 to generate a test pattern for disturbance test is provided within on SDRAM. A test pattern generated with the test pattern generation circuit 1 is given to the related circuit of the selected bank and the test pattern given from a tester is given to the related circuit of the other banks. Thereby, two or more kinds of tests may be done simultaneously.
申请公布号 JP2000215696(A) 申请公布日期 2000.08.04
申请号 JP19990009264 申请日期 1999.01.18
申请人 MITSUBISHI ELECTRIC CORP 发明人 YAMAOKA SHIGERU
分类号 G11C11/401;G01R31/28;G11C11/407;G11C29/06;G11C29/10;G11C29/12;G11C29/36;(IPC1-7):G11C29/00 主分类号 G11C11/401
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