| 摘要 |
PROBLEM TO BE SOLVED: To provide a CMOS semiconductor device, in which the limit of fine fabrication of elements can be relaxed and the pattern size of a CMOS element region be minimized. SOLUTION: This CMOS semiconductor device is provided with an N-type shallow well 12 for forming a PMOS transistor and a P-type shallow sell 21 for forming an NMOS transistor, which are formed selectively on the surface layer of a P substrate 10, a leading area 18 for the N-type shallow well and a leading area 27 for the P-type shallow well, an STI area 29 for separating the CMOS transistor which is formed deeper than the shallow well between a drain region 15 of the PMOS transistor and a drain region 24 of the NMOS transistor and between the N-type shallow well 12 and the P-type shallow well 21 on the surface layer of the P substrate, and STI regions 31 and 32 for separating the CMOS region which are formed deeper than the shallow well on the surface layer of the P substrate.
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