| 摘要 |
PROBLEM TO BE SOLVED: To improve operation speed of a semiconductor circuit and to make the design of the circuit easier by providing a layout which can reduce the parasitic capacitance and wiring resistance of the circuit. SOLUTION: A plurality of gate poly-wirings 5 are drawn in a semiconductor circuit from one sides of rectangular fields 4, and drain wires 6 are drawn in the circuit from the opposite sides of the fields 4. Then source wiring is connected to third wiring through through-holes 7. In addition, the parasitic capacitance of a semiconductor circuit is further lowered by only forming the drain wires 6 near the end sections of the rectangular fields 4.
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