| 摘要 |
PCT No. PCT/JP97/03692 Sec. 371 Date Jun. 11, 1998 Sec. 102(e) Date Jun. 11, 1998 PCT Filed Oct. 14, 1997 PCT Pub. No. WO98/16933 PCT Pub. Date Apr. 23, 1998The circuit arrangement of a memory testing apparatus having a ROM expected value memory is simplified. There are provided a first logical comparator 26 for logically comparing a data read out of a memory under test 200 with an expected value data from a pattern generator 11 as well as a second logical comparator 28 having its one input terminal supplied with a result of the comparison in the first logical comparator 26. The second logical comparator 28 has the other input terminal to be supplied with a ROM expected value data read out of a ROM expected value memory 16. A data read out of a RAM under test is logically compared in the first logical comparator 26 while a data read out of a ROM under test is logically compared in the second logical comparator 28.
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