发明名称 |
Adjustable delay circuit |
摘要 |
An adjustable delay circuit for digital signals includes a series circuit which is disposed between two supply potentials and has at least a first transistor of a first conduction type and second and third transistors of a second conduction type. Control connections of the first and second transistors are connected to a signal input of the delay circuit. One connection of the first transistor, which is remote from the first supply potential, is connected to a signal output. A fourth transistor of the second conduction type is connected in parallel with the third transistor. A first control input is connected to a control connection of the third transistor and a second control input is connected to a control connection of the fourth transistor. The control inputs are used to adjust the delay time of the delay circuit.
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申请公布号 |
US6097233(A) |
申请公布日期 |
2000.08.01 |
申请号 |
US19990228610 |
申请日期 |
1999.01.12 |
申请人 |
SIEMENS AKTIENGESELLSCHAFT |
发明人 |
SCHNEIDER, HELMUT;SCHAFFROTH, THILO;BREDE, RUEDIGER;KRAUSE, GUNNAR |
分类号 |
H03K5/13;(IPC1-7):H03H11/26 |
主分类号 |
H03K5/13 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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