发明名称 |
MOS output buffer with overvoltage protection circuitry |
摘要 |
Either the power-supply potential or a ground potential is applied to a power-supply node through a switch. When a potential higher than the ground potential is applied to an output terminal while the power-supply node is connected to the ground-potential node, the potential of a back gate of a first PMOS transistor incorporated in an output section increases in accordance with the potential of the output terminal, due to a pn-junction provided between the drain and back gate of the first PMOS transistor. At this time, a second PMOS transistor whose source-drain path is connected between the back gate and gate of the first PMOS transistor is turned on, whereby the potential of the back gate of the first PMOS transistor is transferred to the gate thereof.
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申请公布号 |
US6097217(A) |
申请公布日期 |
2000.08.01 |
申请号 |
US19980210761 |
申请日期 |
1998.12.14 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
SHIGEHARA, HIROSHI;KINUGASA, MASANORI |
分类号 |
H03K19/003;H03K19/0175;H03K19/0185;H03K19/0948;(IPC1-7):H03K19/018 |
主分类号 |
H03K19/003 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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