发明名称 |
DRAM with reduced electric power consumption |
摘要 |
A DRAM (Dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.
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申请公布号 |
US6097658(A) |
申请公布日期 |
2000.08.01 |
申请号 |
US19980189148 |
申请日期 |
1998.11.10 |
申请人 |
FUJITSU LIMITED;FUJITSU VLSI LIMITED |
发明人 |
SATOH, YASUHARU;TAKEMAE, YOSHIHIRO;FURUYAMA, TAKAAKI;NAGAO, MITSUHIRO;NIIMI, MASAHIRO |
分类号 |
G11C5/14;G11C11/406;G11C11/4074;(IPC1-7):G11C7/00 |
主分类号 |
G11C5/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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