METHOD FOR FABRICATEING DRAM CELL

摘要

PURPOSE: A method for fabricating a DRAM cell is provided to reduce a parasitic capacitance of a bit line by performing a planarization process before forming the bit line, and to make it easy to form a contact with the planarization process. CONSTITUTION: After forming a gate and a CVD oxide for gate side wall on a substrate, a contact etching is performed by defining a bit line contact together with a node contact. Then, the bit line contact and the node contact are filled with a polycrystalline silicon by growing the polycrystalline silicon selectively so that there is no polycrystalline silicon on a field oxide. Then, a planarization is achieved by filling between the gate on the field oxide with a CVD oxide. A bit line contact is formed by etching back the CVD oxide, and then a bit line polycrystalline silicon(17) and a tungsten silicide(18) and a CVD oxide(19) are formed in sequence. Then, a bit line is defined through a photo lithography process, and a CVD oxide for a bit line side wall is formed and is defined on the whole surface.