DIGITAL PLL CONTROL METHOD USING TRANSITION MODE FOR SYNCHRONIZING

摘要

PURPOSE: A synchronization controlling method is provided to prevent degradation of stability and interference between output clocks by adding an intermediate transition mode. CONSTITUTION: A free-running mode(1) maintains stability of an oscillator in a phase-locked loop. A fast mode(2) enables an output clock of the phase-locked loop to be frequency synchronized with the reference clock. A hold fast mode(3) returns to the fast mode(2) in step(15) if a frequency of the reference clock becomes within an oscillation range of an oscillator, and transits to the free-running mode(1) in step(16) if the frequency of the reference clock is out of the oscillation range. A hold normal mode(5) operates upon the frequency difference between the output clocks in step(17). A fine normal mode(6) operates upon the coincidence between the output clock of the phase-locked loop and the phase of the reference clock in step(13).