| 摘要 |
PURPOSE: A reset signal generating circuit is provided to stably reset a device at a backup mode by generating a reset signal when a halt mode is released. CONSTITUTION: The first signal(11,12,13,14) generator is connected to a power terminal and generates the first reset pulse(PORS) as a power-on-reset signal when a power is supplied. The second signal generator(21-29) receives a halt signal(HLT) and detects an edge of the received halt signal to generate the second reset pulse(HLTT). The third signal generator(31-34) generates an output control signal for setting a period of a reset signal(RES) by synchronizing the first and second reset pulses with a system clock(PI1B). An output part(41-53) receives the first reset pulse(RORS), the second reset pulse(HLTT), and the output control signal and outputs the reset signal(RES) in synchronization with the output control signal when the first or second reset signal is received.
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