发明名称 Trench isolation with suppressed parasitic edge transistors
摘要 An integrated circuit device includes a substrate having a planar surface and isolating trenches etched from the substrate. The isolating trenches form edges and corners with the surface of the substrate. An oxide covers the surface and fills the isolating trenches. The oxide has a thickness at the edges and corners which is greater than its thickness in other areas of the surface of the substrate. Field effect transistors having gate electrodes disposed on the oxide over the edges and corners and over a portion of the other areas of the surface are formed. Formation of parasitic edge transistors is suppressed and thinning of the oxide at the trench edges and corners is prevented because the oxide at the edges and corners is raised with respect to the other areas of the surface, thereby elevating the gate electrode at the edge and corner.
申请公布号 US6097072(A) 申请公布日期 2000.08.01
申请号 US19980081386 申请日期 1998.05.16
申请人 ADVANCED MICRO DEVICES 发明人 OMID-ZOHOOR, FARROKH
分类号 H01L21/762;H01L29/423;(IPC1-7):H01L29/76 主分类号 H01L21/762
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