发明名称 Method to fabricate deep sub- mu m CMOSFETS
摘要 The method of the present invention is a method to fabricate a MOS device without boron penetration. After growing a gate oxide layer, a thin stacked-amorphous-silicon layer (SAS) is deposited over the oxide layer. Subsequently, a lightly nitrogen ion is implanted into the stacked-amorphous silicon layer. The stacked-amorphous silicon layer is patterned to define a gate structure. Then, a light doped ion implantation is performed to dope ions through the gate oxide layer into the substrate to form lightly doped source and drain regions. A dielectric layer is formed over the gate structure and the gate oxide layer, and the dielectric layer is etched to form sidewall spacers. Next, a second ion implantation is performed to dope ions into the substrate to form source and drain. Finally, a thermal annealing is performed on the stacked-amorphous silicon gate and the substrate. The nitrogen ions in the stacked-amorphous silicon gate are segregated into the gate oxide layer to act as a diffusive barrier, the stacked-amorphous silicon gate being convert into ploy silicon gate and thereby forming shallow source and drain junction in the substrate.
申请公布号 US6096614(A) 申请公布日期 2000.08.01
申请号 US19980020229 申请日期 1998.02.06
申请人 TEXAS INSTRUMENTS - ACER INCORPORATED 发明人 WU, SHYE-LIN
分类号 H01L21/28;H01L21/8238;H01L29/51;(IPC1-7):H01L21/336 主分类号 H01L21/28
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