| 摘要 |
PURPOSE: A clock supplying apparatus is provided to supply a stable system synchronous clock to each device constituting a host digital terminal(HDT). CONSTITUTION: A reference timing selecting part(310) performs external clock, ATRU signal, and clock operation mode selecting operations. A DP-PLL part(320) outputs a frequency having 19.44MHz. An external clock transmitting and receiving part(330) receives two 2.048Mbps signals from an external clock source to extract a clock and data of each received signal. The external clock transmitting and receiving part(330) detects an LOS state to transfer LOS information to a reference timing controlling/monitoring part(350) and supplies a clock signal to an external device. A driver part(340) transfers the 19.44MHz clock signal and a 25.92MHz cell bus clock signal to each device. The reference timing controlling/monitoring part(350) receives a reference clock selection signal(REF_SEL) from a micro controller unit(MCU)(300) to transfer the received signal to the reference timing selection part(310) and monitors whether an error arises at each clock mode to then transfer monitored information to a central processing unit(CPU). An MCU connecting part(360) interconnects the MCU(300) and the clock supplying part(215) and controls a register part(365). An LED part(364) displays an operation state of the clock supplying device(215). A divider(370) divides the 19.44MHz signal from the DL-PLL part(320) to transfer the divided signal to the reference timing controlling/monitoring part(350).
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