| 摘要 |
PURPOSE: A high-speed phase-locked loop is provided to prevent errors in an initial operation by using a feedback loop and a self-delay time measuring route. CONSTITUTION: A high-speed phase-locked circuit has a measurement controller(40) with a self-phase measure circuit(42) and a measure delay array(43); and a register controller(41) with a phase detecting block(44), a shift register array(45), a variable delay array(46) and a delay compensating block(47). The self-phase measure circuit(42) measures phases of an RCLK signal and an RCLK signal to latch an enable signal in a rising edge of the RCLK signal to output an MB(Measure Begin) signal, and outputs an ME(measure End) signal. The measure delay array(43) includes n number of measure delay units, and outputs delay time compensation cycle determining signals(MQ1,...,MQn). The phase detecting block(44) outputs an SHR(shift right) signal, an SHL(shift left) signal, a clock lock signal and two-division clock signal. The shift register array(45) outputs delay time compensating signals(Q1,...,Qn). The variable delay array(46) is delayed by the delay time compensating signals(Q1,...,Qn). The delay compensating block(47) receives a delayed clock(DCLK) to carry out feedback of an FCLK.
|
