| 摘要 |
A phase locked loop circuit that rapidly synchronizes an internal synchronizing signal with the reference signal includes a phase detector detecting the difference between the signals, a current generator, a charge pump controlled by the phase detector generating voltage by converting current from the current generator into a control voltage, a lock detector detecting whether the phase difference between the signals is within a predetermined range, a loop filter with variable capacitance that is charged and discharged by the control voltage from the charge pump and which changes capacitance is response to lock and unlock signals from the lock detector, and a voltage controlled oscillator converting the control voltage into the internal synchronizing signal. When the phase difference between the signals is within the predetermined range, the lock detector outputs a "lock" signal to the loop filter, and the capacitance of the filter is set to be large. When the phase difference between the signals is outside of the predetermined range, the lock detector outputs a "unlock" signal to the loop filter, and the capacitance of the filter is set to be small. By changing the capacitance of the loop filter, lock-up time is reduced. The capacitance within the loop filter is maintained at the control voltage even when it is not part of the filter, preventing a drop in the control voltage induced by the adding of capacitance.
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