PHASE CONTROL CIRCUIT OF CLOCK SIGNAL FOR SYNCHRONOUS TRACKING IN WIRELESS COMMUNICATION SYSTEM

摘要

PURPOSE: A phase adjusting circuit is provided to be capable of finely adjusting a phase of a clock signal reproduced for an exact synchronization with a transferred clock signal. CONSTITUTION: A clock speed adjusting part(100) determines a rate for dividing a clock source signal in the case where a system supports various clock speeds. A clock divider(102) divides a clock source signal from an oscillator according to the determined rate. An M-stage register part(104) stores the divided clock signal at a rising edge of the clock source signal and generates a bus signal as a reference signal. A clock adjustment determining part(106) receives a synchronous tracking result signal and determines phase adjustment direction and amount of a clocks signal. A phase adjusting part(108) has a previously set resister value in a register and receives an enable signal(EN) and a direction signal(DIR) from the clock phase determining part(106). The phase adjusting part(108) rotates the stored register value by one bit in a right direction when the direction signal is at a logic high and by one bit in a left direction when the direction signal is at a logic low. An AND/OR gate circuit(110) generates a reproduction clock signal in response to the multi-bit reference signal from the M-stage register part(104) and a multi-bit data signal from the phase adjusting part(108).