Microprocessor with common bus for memory and peripheral circuit having data latch generator

摘要

Disclosed herein is a microcomputer of the present invention. The microcomputer comprises a memory, a peripheral circuit including a circuit whose change of state is fast and which latches data to be held by the circuit therein in response to a data latch signal and outputs the latched data therefrom in response to a first read control signal and a data latch signal generating circuit supplied with the first read control signal so as to generate the data latch signal whose signal time interval is shorter than that of the first read control signal, and a central processing unit which is connected to the memory and the peripheral circuit through a common bus and which outputs an address signal for specifying the circuit and the first read control signal to the common bus to perform access to the circuit and outputs an address signal for specifying the memory and a second read control signal shorter than the first read control signal in signal time width to the common bus to make access to the memory