| 摘要 |
PROBLEM TO BE SOLVED: To obtain a data processor which is free of disadvantages resulting from the provision of individual memories for data and instructions by enabling accessing of a storage location in a memory through both a data access port and an instruction access port. SOLUTION: A data address bus DA of a Harvard-type central processing unit 4 passes a data address signal to a data address decoder 6. Similarly, the instruction address bus IA passes an instruction address to an instruction address decoder 8. The data address decoder 6 and instruction address decoder 8 operate to decode the address inputs respectively and select rows 12 and 14 of memory cells in a memory of 1st level to be accessed by a data side and an instruction side. The data allows read and write access to the row 12 of the memory cells. The instruction side allows read-only access to the row 14 of memory cells.
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