| 摘要 |
PROBLEM TO BE SOLVED: To reduce a chip area. SOLUTION: When a specified period A elapses after an end edge of synchronizing signals, the output voltage of an operational amplifier 1 slightly rises to the left side voltage Vdd/2 of a second capacitor 13. Then, first and second capacitors 3 and 13 form a closed loop and the negative terminal voltage of the operational amplifier 1 rises in the range of <=0.75 Vdd corresponding to the capacity ratio of the first and second capacitors 3 and 13. Thereafter, when synchronizing signals arrive, the negative terminal voltage of the operational amplifier 1 rises to 0.75 Vdd and the output voltage of the operational amplifier 1 lowers corresponding to a time constant determined by the resistance value of resistors 8 and 9 and the first capacitor 3 and becomes a sync level at the end edge of the synchronizing signals.
|
