发明名称 LAMINATED CHIP BEAD
摘要 PROBLEM TO BE SOLVED: To reduce the size of a laminated chip bead and to increase the impedance of the bead by forming conductive layers at a rate of one or more turns per one layer, and, at the same time, controlling the thickness of magnetic layers to a specific multiple of that of the conductive layers or thinner. SOLUTION: A laminated chip bead 1 has a rectangular parallelepiped chip body 10 formed by alternately laminating magnetic layers 2 and conductive layers 3 upon another. The conductive layers 3 are formed in a pattern and, in addition, adjacent conductive layers 3 are electrically connected to each other so as to form coils. On the surface of the chip body 10, external electrodes 5 which are electrically connected to the conductive layers 3 are provided. The number of turns of each conductive layer 3 is controlled to one or more turns and the dimension of the layer 3 is adjusted to 5-30μm in thickness and about 10-350μm in line width. The end sections 31 and 33 of adjacent paired conductive layers 3 and 3 are electrically connected to each other through the through hole of the magnetic layer 2 interposed between the layers 3 and 3. In addition, the thickness of the magnetic layers 2 is adjusted to 0.5-2 times as thick as that of the conductive layers 3. Usually, the thickness of the layers 2 is adjusted to about 8-40μm.
申请公布号 JP2000208330(A) 申请公布日期 2000.07.28
申请号 JP19990370115 申请日期 1999.12.27
申请人 TDK CORP 发明人 KANAGAWA YOICHI
分类号 H01F17/06;H01F17/00;(IPC1-7):H01F17/06 主分类号 H01F17/06
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