| 摘要 |
PROBLEM TO BE SOLVED: To increase the degree of high integration of a NAND nonvolatile ferroelectric memory cell by fixing the voltage induced in a bit line, improving the operational characteristics of the cell, and minimizing the layout area by providing a ferroelectric capacitor between each work line and the output terminal of the transistor of each word line. SOLUTION: In a NAND nonvolatile ferroelectric memory cell, NMOS transistors T1-T5 are connected in series and a bit line B/L is formed in the direction in which the transistors T1-T5 are formed. The source of the transistor T1 and the drain of the transistor T5 are connected to the bit line B/L. Word lines are connected to the gates of the transistors other than the transistor T5 and a WEC signal line is connected to the gate of the transistor T5. WEC signals are such signals that only maintain activated states in a write mode, but maintain nonvolatile states in a readout mode. Ferroelectric capacitors FC1-FC4 are respectively connected between the word lines connected to the gates of the transistors T1-T4 and the drains of the transistors T1-T4.
|
