| 摘要 |
<p>PROBLEM TO BE SOLVED: To detect synchronization establishment and step-out in an early stage by providing two monitoring means and detecting synchronization by the detection confirmation of one of them for each frame. SOLUTION: This device is provided with a shift register 1 constituted of m+1 stages when reception signals constitute one frame by m bits, an AND gate 2 for inputting the inverted output of the first stage and the output of the (m+1)-th stage of the shift register 1, a counter 3 for 0/1 detection for performing counting based on the output of the AND gate 2, the AND gate 4 for inputting the output of the first stage and the inverted output of the (m+1)-th stage of the shift register 1 and the counter 5 for the 1/0 detection for performing counting based on the output of the AND gate 4. In such a manner, by providing the counters 3 and 5 for 0/1 and 1/0 detection respectively for respectively monitoring whether or not the frame for which an F bit (prescribed position of frame) is 1 comes after the frame for which the F bit is 0 and whether or not the frame for which the F bit is 0 comes after the frame of 1, monitoring is performed for each frame and decision is performed based on the detected result.</p> |
