| 摘要 |
PROBLEM TO BE SOLVED: To readily realize contact to a stopper layer which supplies potential to a P-type well and an N-type well by raising wiring flexibility of an ALA layer by directly connecting an impurity diffusion region which is output of a logic gate of a preceding stage and a gate electrode of a following stage by a salicide bridge. SOLUTION: Input IN1 is supplied to a gate of a P-channel MOS transistor P1 and an N-channel MOS transistor N1 constituting an inverter through an ALA layer 6. A gate electrode layer 2 is constituted of polycrystalline silicon of a first layer which reacts on high melting point metal in a following salicide process. A drain diffusion layer which becomes output of an inverter and a one-side gate electrode layer 2 of a following stage NAND gate are connected by a salicide bridge wherein a selective sidewall removal at a THLA 8 is used. Input IN2 and a two-stage inverter (MOS transistors P5, N5 and P4, N4) are constituted similarly.
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