| 摘要 |
PROBLEM TO BE SOLVED: To increase the data processing speed of a data processor by eliminating unnecessary bus wait. SOLUTION: A data processor is provided with a control circuit 16, plural CPUs 1-3, and plural system buses 17A-17C. The processor is also provided with memories 10-15 and plural memory bus selectors 4-9 which can selectively connect the memories 10-15 to the buses 17A-17C. The control circuit 16 generates plural select signals for selectively connecting the memories 10-15 to the buses 17A-17C and gives the signals to the selectors 4-9. The selectors 4-9 selectively connect the memories 10-15 to the buses 17A-17C in response to the select signals. The CPUs 1-3 process data by performing access to the memories 10-15 in parallel.
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