Non-volatile ferroelectric memory has main cell array with sub-cell arrays with global main, reference bit lines, local main, reference bit lines, switches, controllers, part word line driver

摘要

The memory has a main cell array (71) with a number of sub-cell arrays containing global main bit lines and at least one pair of global reference bit lines, local main bit lines and reference bit lines, switches between local and global bit lines, a reference bit line controller (77), a main bit line controller (75) and a part word line driver (73) on one side of the main cell array