CMOS optimization method utilizing sacrificial sidewall spacer

摘要

An ultra-large scale CMOS integrated circuit semiconductor device is processed after the formation of the gates and gate oxides by N-type dopant implantation to form N-type shallow source and drain extension junctions. Spacers are formed for N-type dopant implantation to form N-type deep source and drain junctions. A higher temperature rapid thermal anneal then optimizes the NMOS source and drain extension junctions and junctions, and the spacers are removed. A thin oxide spacer is used to displace P-type dopant implantation to P-type shallow source and drain extension junctions. A nitride spacer is then formed for P-type dopant implantation to form P-type deep source and drain junctions. A second lower temperature rapid thermal anneal then independently optimizes the PMOS source and drain junctions independently from the NMOS source and drain junctions.