Semiconductor integrated circuit having controlled output resistance of an output buffer circuit

摘要

An object is to provide a semiconductor integrated circuit capable of controlling the output resistance value of an output buffer circuit always at a given value without deteriorating the data transmission quality. D latches (60-63, 65-68) in latch circuit portions (16, 17) in an output resistance control output buffer circuit (2) receive an output resistance control trigger signal (STRB) in common at their respective T inputs. The D latches (60-63) also receive pull-up bit control signals (U0-U3) at their respective D inputs, and the D latches (65-68) also receive pull-down bit control signals (D0-D3) at their respective D inputs. The output resistance value of transistors (QU0-QU3) and transistors (QD0-QD3) is controlled with the data latched in the latch circuit portions (16, 17), respectively. The output resistance control trigger signal (STRB) rises to "H" after a sufficient time has passed after an output resistance control signal determining period in which the pull-down bit control signals (D0-D3) and the pull-up bit control signals (U0-U3) are determined.