| 摘要 |
PURPOSE: A data processor is provided to lower the access time at generating the Write miss in the cache memory unit, by sending the data to the external main memory at the beginning without sending the data to the external main memory via the write-back buffer. CONSTITUTION: A data processor comprises a CPU(21), a main memory unit(22), a cache memory unit(23), an U/V detect and control unit(24) and a multiplexor(25). The CPU(21) outputs the reset signal to the cache memory unit(23) and sends the enable signal to the U/V detect and control unit(24). The cache memory unit(23) has the associative cache structure and outputs the entry signal to the multiplexor(25) when receiving the enable signal from the U/V detect and control unit(24). The U/V detect and control unit(24) receives the enable signal from the CPU(21), sends the enable signal to the main memory unit(22) and the cache memory unit(23) and outputs the selection signal to the multiplexor(25). The multiplexor(25) receives the selection signal and the output data from the CPU(21) and the cache memory unit(23) and outputs the selection signal and the data to the external main memory unit(22).
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