LAYOUT STRUCTURE OF TEST PATTERN OF SEMICONDUCTOR DEVICE

摘要

PURPOSE: A layout structure of a test pattern of a semiconductor device is provided to precisely evaluate junction leakage current characteristics due to a silicide film cladded on source and drain areas by forming the source and drain areas in an equal condition as in a semiconductor chip when plasma etching. CONSTITUTION: A semiconductor substrate is defined with an active area and an isolation area. A first gate(65) formed of a long polycide strip is traversing the active region(63) and has both end parts extended to the isolation region. First and second impurity diffusion areas(66) are formed in the finger type island in a source area(64a) and/or a drain area(64b) and divided by the first gate, A pair of first dummy gates are formed on the first impurity diffusion area and a pair of second dummy gates are formed in the second impurity diffusion area. A plurality of contacts(67) are formed in a predetermined area of the first gate and the active area.