| 摘要 |
PURPOSE: A Digital Frequency and Phase Lock Loop(DEPLL) is provided to stabilize the system when channels are frequently and suddenly changed by enabling automatic conversion of phase lock loop. CONSTITUTION: A Digital Frequency and Phase Lock Loop(DEPLL) includes a frequency error detecting section(105) which detects frequency errors from I signals outputted by a multiplicator(103), a limitation pad(106) which outputs only code information of pilot signals by hard limiting pilot signals, a low frequency filter(107) which filters Q signals from the multiplicator(103), and a phase difference detector(109) which detects differences in outputted signals and provides it to a numerical controlling oscillator(104). The device enables users to easily install a hole hardware by providing a device that has a less number of Finite Impulse Response Filters and multiplicators.
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