发明名称 Floating point arithmetic unit including an efficient close data path
摘要 An execution unit configured to execute vectored floating point and integer instructions. The execution unit may include an add/subtract pipeline having far and close data paths. The far data path is configured to handle effective addition operations, as well as effective subtraction operations for operands having an absolute exponent difference greater than one. The close data path is configured to handle effective subtraction operations for operands having an absolute exponent difference less than or equal to one. The close data path includes an adder unit configured to generate a first and second output value. The first output value is equal to the first input operand plus an inverted version of the second input operand, while the second output value is equal to the first output value plus one. The two output values are conveyed to a multiplexer unit, which selects one of the output values as a preliminary subtraction result based on a final selection signal received from a selection unit. The selection unit generates the final selection signal from a plurality of preliminary selection signals based on the carry in signal to the most significant bit of the first adder output value. Selection of the first or second output value in the close data path effectuates the round-to-nearest operation.
申请公布号 US6094668(A) 申请公布日期 2000.07.25
申请号 US19980049893 申请日期 1998.03.27
申请人 ADVANCED MICRO DEVICES, INC. 发明人 OBERMAN, STUART F.
分类号 G06F7/57;G06F9/30;G06F9/302;G06F9/318;G06F9/38;H03M7/24;(IPC1-7):G06F7/42 主分类号 G06F7/57
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