| 摘要 |
A clock signal control circuit includes a divider dividing an external clock signal into multiple phase clock signals, timing difference dividers connected to the divider for dividing a difference in phase of pulses between the multiple phase clock signals having different phases from each other to generate different phase clock signals, a single multiplexer connected to the timing difference dividers for multiplexing the different phase clock signals to generate multiplexed clock signals, and a synthesizer connected to the multiplexers for synthesizing the multiplexed clock signals into a single multiplied clock signal.
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